The present invention relates to a data processing device, a microcontroller, and a self-diagnosis method of the data processing device, in particular to a data processing device, a microcontroller, and a self-diagnosis method of the data processing device which can perform a read-modify-write process.
In a data processing device including an arithmetic circuit (for example, CPU: Central Processing Unit) and a memory, the arithmetic circuit accesses the memory, so that the data processing device can perform various processes. There are data processing devices which include a read-modify-write circuit that performs a read-modify-write process. Here, the read-modify-write process is a process where data read from the memory is modified and the modified data is written back to the memory. It is possible to reduce the latency of the data processing device by disposing the read-modify-write circuit realizing such a process near the memory.
Nowadays, such a data processing device is used in various apparatuses and a high reliability of the data processing device is required. For example, when the data processing device is used as an in-car microcomputer, a high self-diagnosis rate is required in an international functional safety standard. Therefore, to improve the reliability of the data processing device, for example, the data processing device is required to have a duplex structure.
Japanese Unexamined Patent Application Publication No. 2009-282849 discloses a technique related to a microcomputer including duplicated CPUs and duplicated ECC (Error Checking and Correction) circuits. The technique disclosed in Japanese Unexamined Patent Application Publication No. 2009-282849 can determine which ECC circuit of the duplicated ECC circuits fails, so that the reliability of the microcomputer is improved.
Japanese Unexamined Patent Application Publication No. 2009-289170 discloses a technique related to a data processing device which can increase the speed of the read-modify-write process. Japanese Unexamined Patent Application Publication No. Hei6 (1994)-324950 discloses a technique related to a memory control circuit which can correct an error even if a part of a memory fails in a case in which the memory outputs a plurality of data bits.